Two targets with the same name in a Makefile

Question

I was wondering what happens if there is 2 targets with the same name in a Makefile: According to This question, Having 2 targets with the same name throws warnings. However, i don't understand how this Makefile in openwrt works: In `include/package.mk`: ``` define Build/DefaultTargets $(if $(QUILT),$(Build/Quilt)) $(if $(USE_SOURCE_DIR)$(USE_GIT_TREE),,$(if $(strip $(PKG_SOURCE_URL)),$(call Download,default))) $(call Build/Autoclean) download: $(foreach hook,$(Hooks/Download), $(call $(hook))$(sep) ) ``` Note here the call to `Download`function in the 3rd line and the definition of the target `download` in the 6th line. By having a look at the definition of the function `Download` in `include/download.mk`: ``` define Download $(eval $(Download/Defaults)) $(eval $(Download/$(1))) $(foreach FIELD,URL FILE $(Validate/$(call dl_method,$(URL),$(PROTO))), ifeq ($($(FIELD)),) $$(error Download/$(1) is missing the $(FIELD) field.) endif ) $(foreach dep,$(DOWNLOAD_RDEP), $(dep): $(DL_DIR)/$(F…

Accepted Answer

If a target is specified without a recipe, it's simply adding a dependency to the target. You're allowed as many of these as you want. So the following is valid:

```
foo: dep1 dep2

foo: dep3
    recipe1
```

In which case, if dep1, dep2, or dep3 are rebuilt, then recipe1 is run. But this is not:

```
foo:
    recipe1

foo:
    recipe2
```

At this point make wouldn't know which recipe to run, and/or in which order, so Make complains. (note that you can have multiple definitions for pattern rules, in which case make chooses the first one that matches, but that's not allowed with static rules)

Two targets with the same name in a Makefile

Solution

Problem