Multiple if statements in makefile conditionals

Question

The make documentation says the syntax of a complex conditional is as follows: ``` conditional-directive-one text-if-one-is-true else conditional-directive-two text-if-two-is-true else text-if-one-and-two-are-false endif ``` But I don't understand how to use this syntax to rewrite the following piece of code: ``` ifeq ($(option), 1) CC=gcc @echo use gcc else ifeq($(option), 2) CC=clang @echo use clang else CC=mipsel-linux-gcc @echo use mipsel-linux-gcc endif #first target foo: ; ```

Accepted Answer

IMHO, `ifeq` statements take too much space, harder to type and read. A better alternative:

```
CC.1 := gcc
CC.2 := clang
CC := $(or ${CC.${option}},mipsel-linux-gcc)
$(info "Using ${CC}")
```

Multiple if statements in makefile conditionals

Solution

Problem