Makefile dependent targets based on current target

dependencies, gnu, makefile, target

Solution

See Multiple Targets in a Rule and Multiple Rules for One Target from the GNU Make Manual:

$ cat Makefile.common
all: Target0 Target1

Target0: Deps0
Target1: Deps1

Deps%:
        @echo 'Making $@'

Target0 Target1:
        @echo 'Making $@ from $^'

$ make -f Makefile.common
Making Deps0
Making Target0 from Deps0
Making Deps1
Making Target1 from Deps1

Problem

I have the following code in my Makefile: `Target0: Deps0 Common Rule to build Target Target1: Deps1 Common Rule to build Target ...` My question is since all the targets have a common rule is there any way to combine the targets into a single target and specify target specific dependencies?

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