System Verilog Clocking block
system-verilog
Solution
As the error message says, you have to define the clocking block as default:
default clocking cb_counter @(posedge Clock);
Full code here: http://www.edaplayground.com/x/37_
The SV 2012 standard specifies that the `##n` operator can only be used if there is a default clocking block defined for the module/program/interface, otherwise it wouldn't be able to know what clock event to use for the delay.
Problem
I am trying to perform a simple test with demo code of Clocking block, but encountered the error. The code could be find at "EDA playground" http://www.edaplayground.com/x/3Ga And the error says: ** Error: testbench.sv(38): A default clocking block must be specified to use the ##n timing statement. ** Error: testbench.sv(40): A default clocking block must be specified to use the ##n timing statement. I think the clocking block has already been specified in the code. Any Help?