SystemVerilog foreach syntax for looping through lower dimension of multidimensional array

arrays, foreach, multidimensional-array, system-verilog

Solution

You can do this:

$display("Loop through i=2");
begin
  automatic int i = 2;
  foreach (my_req[,j]) begin // notice the "," before j
    $display("i:%0d,j:%0d", i, j);
  end
end

Working code on EDA Playground: http://www.edaplayground.com/x/2Qn

Problem

What is the standard way of looping through the lower dimension of a multidimensional array? With the higher dimension fixed. In the following example: ``` automatic int i = 2; foreach (my_req[i][j]) begin // <-- WARNING $display("i:%0d,j:%0d", i, j); end ``` I see the warning: ``` ** Warning: testbench.sv(16): (vlog-LRM-2897) Using non-standard foreach loop variable list syntax. ``` Full code example on EDA Playground: http://www.edaplayground.com/x/nh

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