make with dynamic target names
gnu-make, makefile
Solution
The behavior you described is the behavior you want from the make system and this is why it is so loved by many and scales so well.
`make test.cpp` does not work because what you want is `make a.out`
Try starting from a simple but correct makefile and evolve it to your needs
To trigger the compilation remove `test.o` and say `make test.o`, or say `touch test.cpp` and then again `make test.o`. If you do not want intermediate object files (I tell you - you do want them) you can apply the above advice replacing `test.o` with `a.out`.
You are trying to push where you should be pulling :-)
As @MadScientist reminded in his comment, one of useful features of GNU Make is a vast set of default rules which may save quite a bit of boilerplate when you don't need fine control of each step.
Problem
I know that I can use the automatic variable `$@` from within a target in a makefile to retrieve the name of the current target. Now I wonder whether it is possible to have a makefile that looks like this:... ``` $@: g++ $@ && ./a.out ``` The idea is that typing `make test.cpp` should run `g++ test.cpp && ./a.out` where as `make main.cpp` should run `g++ main.cpp && ./a.out`. I see that wildcards might be strongly related to my problem. However, a makefile like this: ``` *.cpp: g++ $@ && ./a.out ``` does indeed create the appropriate targets, but running `make test.cpp` with such a makefile yields `make: >>test.cpp<< is already up-to-date` - without the compilation taking place.