Register Design in VHDL

vhdl

Solution

So let's first look at some issues in your code:

- You have a 32 bit input, and 1 bit output, but presumably that's just an accident.

- When you're not reseting the register, and we're not on the rising_edge, you unconditionally set the output to `'0'`. That isn't modeling a register, so let's remove that.

- We can also simplify your internal logic by just assigning `d` to `q` at the appropriate time. (This makes the 32-bit logic much simpler as well).

- We can write `clk'event and clk='1'` as just `rising_edge(clk)`.

- There are some small syntax issues in your port declaration. Note that the last member does not end in a semicolon, and the port declaration itself ends in a `);`

So, this causes us to have for a one bit register:

ENTITY register1 IS PORT(
    d   : IN STD_LOGIC;
    ld  : IN STD_LOGIC; -- load/enable.
    clr : IN STD_LOGIC; -- async. clear.
    clk : IN STD_LOGIC; -- clock.
    q   : OUT STD_LOGIC -- output.
);
END register1;

ARCHITECTURE description OF register1 IS

BEGIN
    process(clk, clr)
    begin
        if clr = '1' then
            q <= '0';
        elsif rising_edge(clk) then
            if ld = '1' then
                q <= d;
            end if;
        end if;
    end process;
END description;

And if we wanted to extend this to 32 bits:

ENTITY register32 IS PORT(
    d   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    ld  : IN STD_LOGIC; -- load/enable.
    clr : IN STD_LOGIC; -- async. clear.
    clk : IN STD_LOGIC; -- clock.
    q   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- output
);
END register32;

ARCHITECTURE description OF register32 IS

BEGIN
    process(clk, clr)
    begin
        if clr = '1' then
            q <= x"00000000";
        elsif rising_edge(clk) then
            if ld = '1' then
                q <= d;
            end if;
        end if;
    end process;
END description;

Problem

I'm having some troubles in designing a 1-bit and 32-bit register in VHDL. Main inputs of the register include clock (clk), clear (clr), load/enable(ld) signals and an n-bit data (d). The n-bit output is denoted by (q). So far I believe to have made a 1-bit register, here is my code: ``` LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY register32 IS PORT( d : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- input. ld : IN STD_LOGIC; -- load/enable. clr : IN STD_LOGIC; -- async. clear. clk : IN STD_LOGIC; -- clock. q : OUT STD_LOGIC; -- output. END register32; ARCHITECTURE description OF register32 IS BEGIN process(clk, clr, ld) begin if clr = '1' then q <= '0'; elsif d = '1' and ld = 1 and clk'event and clk='1' then q <= '1'; elsif d = '0' and ld = 1 and clk'event and clk='1' then q <= '0'; else q <= '0'; end if; end process; END description; ``` If this is correct for a 1-bit register, how would I make it into a 32 bit one. Some help would be greatly appreciated.

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