How to check whether a UVM analysis port is connected?

system-verilog, uvm

Solution

It is not a UVM requirement that analysis ports are connected. However, some UVM components will not function correctly when their analysis ports are unconnected.

For those cases, I recommend checking the analysis import connections during the `end_of_elaboration_phase`:

`CHECK_PORT_CONNECTION(my_analysis_imp)

Where the above macro is defined like:

`define CHECK_PORT_CONNECTION(PORT) \
  begin \
    uvm_port_list list; \
    PORT.get_provided_to(list); \
    if (!list.size()) begin \
      `uvm_fatal("AP_CONNECT", \
        $sformatf("Analysis port %s not connected.", PORT.get_full_name())); \
    end \
  end

Complete working example with one connected port and one not connected: http://www.edaplayground.com/x/2YG

Problem

Oftentimes our UVM simulations fail with signatures that we end up debugging to unconnected analysis ports. Is there a way to check up front whether the analysis ports are connected before the `run_phase`?

Original source