Overriding explicit rules in Makefiles

Question

I have a Makefile system that dynamically generates rules to build lists of files for different platforms. For various reasons implicit rules cannot be used as there is no common pattern to apply, but rather the output of various functions over file lists. Now I'm trying to add automatic dependency generation in a way that it's triggered only for the targets that are needed to be built. The normal way to do this is to define implicit rules that generate dependencies and then include or define explicit rules requiring these dependencies as prerequisites for the same target (see http://mad-scientist.net/make/autodep.html for an example). This works because make automatically overrides implicit rules with explicit versions of the same rule without complaining. However, since I have no option to use implicit rules I'm trying to figure out a way to do this. I see only two approaches: - Dynamically rewrite explicit rules and get a "warning: overriding commands for target" for each one. - Fi…

Accepted Answer

The short answer is no, there is no way to replace explicit rules without getting that message (well of course since GNU make is open source, you could modify the code and build your own version).

The longer answer is that I think your initial assumption is incorrect. I don't understand what you mean by this works because make automatically overrides implicit rules with explicit versions of the same rule without complaining.

What you appear to be thinking of is prerequisite statements that do not have recipes, like:

```
%.o : %.c
        $(CC) ...

foo.o: foo.c foo.h bar.h
foo.o: biz.h baz.h
```

etc. The rule in GNU make is that there can be only one rule defining a recipe for any given target (single-colon targets anyway). There can be as many rules defining only prerequisite relationships, without defining recipes, as you like. When these prerequisite-only rules are seen they simply append the additional prerequisites to the list of current prerequisites.

And, there is no difference between implicit or explicit rules here; for example the above example could be written:

```
foo.o : foo.c
        $(CC) ...

foo.o: foo.c foo.h bar.h
foo.o: biz.h baz.h
```

and that's perfectly legal and will not give you any warnings.

It seems that there is a problem in your makefile and you've done a bit of leaping to conclusions about what the problem is, then instead of describing the problem itself you're asking how to work around the conclusion. If you back up and show us an example of the makefile where you're seeing the warning generated (and show how you invoke make and past the warning you get), we can probably better assist you.

Overriding explicit rules in Makefiles

Solution

Problem