How do I access an internal reg inside a module?

system-verilog, verilog

Solution

You don't need to use `bind`:

module DUT;
bit clk;
initial begin
    repeat (5) begin
        #5 clk = 0; 
        #5 clk = 1;
    end
end

always @(posedge clk) begin
    $display ("[Time %0t ps] IntReg value = %x", $time, DUT.IntModule.IntReg);
end

IntModule IntModule ();
endmodule

module IntModule;
    reg IntReg = 1;
endmodule

Output:

[Time 10 ps] IntReg value = 1
[Time 20 ps] IntReg value = 1
[Time 30 ps] IntReg value = 1
[Time 40 ps] IntReg value = 1
[Time 50 ps] IntReg value = 1

Problem

I have this architechture/topology in Verilog: How can I access the internal reg `IntReg`, that isn't a input/output in `IntModule`, in SystemVerilog? ``` always @(posedge clk) begin $display ("[Time %0t ps] IntReg value = %x", $time, DUT.IntModule.IntReg); end ``` Can I use bind? How?

Original source