How can I set a full variable constant?
system-verilog, verilog
Solution
You can use the replication operator to construct bit vectors.
{a{b}} produces a vector with a copies of vector b.
In your case this would be:
a = {`SIZE{1'b1}};
Problem
When the number size is variable and thus must be set by parameter, how can I set the maximum number? In the following, the result must be "FFFF", but the simulator returns just "F". Could anyone fix this problem? ``` `define SIZE 10 module tb1; reg [15:0] a; initial begin a = `SIZE'hF; $display("a=%h",a); end endmodule ```