How to 'assign' a value to an output reg in Verilog?

verilog

Solution

The `assign` statement is used for driving `wire`s.

If you've somethings declared as a `reg`, then you have to give it values inside a procedure ( `always` or `initial` blocks ). It's best practice to only set values of `reg`s in the same `always` block. eg:

always @( * ) begin // combo logic block
   if( some_condition ) begin
      icache_ram_rw = 1'b0;
   end else begin
      icache_ram_rw = something_else;
 end

There are important differences between `reg`s and `wire`s that you should read up on.

I've a feeling though that you'll need some clocked logic if you're driving RAM signals. In this case, you'll need code that looks something like this:

// some parameter definitions to make logic 'read' clearer.
localparam READ = 1'b0; 
localparam WRITE = 1'b1;

// standard clocked logic 'template' that synthesis tools recognise.
always @( posedge clk or negedge resetb )
  if( !resetb ) begin  // asynchronous active low reset
     icache_ram_rw <= READ;
  end else if( some_enable_condition ) begin
     icache_ram_rw <= WRITE;
  end else begin
     icache_ram_rw <= READ;
  end

Problem

( insert really basic question disclaimer here ) More specifically, I have the following declaration: ``` output reg icache_ram_rw ``` And in some point of the code I need to put the zero value in this reg. Here's what I've tried and the outcomes: ``` assign icache_ram_rw = 1'b0; ( declarative lvalue or port sink reg icache_ram_rw must be a wire ) icache_ram_rw <= 1'b0; ( instance gate/name for type "icache_ram_rw" expected - <= read ) ``` How do I do it after all?!

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