How to reuse an instantiated module in verilog with updated inputs
verilog
Solution
Inputs are continuous time signals. The module instantiation is not a method call but constantly executing logic, therefore any change in `in1` value will be passed directly to instance `name_abc`.
If you mean to use the same module (hardware) but being able to switch between 2 data streams, imply a mux in front of it.
wire connect_to_abc_in;
assign connect_to_abc_in = (select) ? in1 : in1_alternative ;
Problem
I have a module : ``` module abc( input in1, input in2, output in3 ); ``` Instantiating this module in another main module: ``` abc name_abc(in1, in2, out); ``` Now in1 is changed based on some other signal. From what I understand, the instantiation would have created a block of the logic, now I want to use the block already created but with different inputs or updated inputs. Is there a way to do this in verilog? What I want to do is : ``` abc name_abc(in1_updated, in2, out); ```