VHDL initialize vector (the length is not a multiple of 4) in hex
initialization, stdvector, vhdl
Solution
a possible workaround is to write multiples of 4 bits as hex value and add the rest in binary, e.g.:
signal v: std_logic_vector(9 downto 0) := "01" & X"1A";
Problem
For example, I have a vector which length is 10. How can I initialize it in hex. (The synthesize tool complains size mismatch as it thinks the hex value is a multiple of 4) ``` signal v : std_logic_vector (9 downto 0) := x"11A"; ``` Many thanks! Nigong