Makefile rule using the automatic variable $^ without dependencies
makefile, prerequisites, variables
Solution
`$^` contains all the prerequisites of the target, not just the ones that are mentioned with the rule itself. The same file can appear as a target several times in rules with no commands:
sometarget: dependency1
…
sometarget: dependency2
assemble -o $@ $^
…
sometarget: dependency3
The dependencies of `sometarget` are `dependency1`, `dependency2` and `dependency3`, and when the `assemble` command is invoked by `make sometarget`, it will receive all three as arguments.
Here, `$^` will contain all `$(CLT_OBJECT_FILES)` or `$(SRV_OBJECT_FILES)` depending on which target the command is executed for.
Problem
I learnt from the GNU Make manual that the sign `$^` is an automatic variable which represents the names of all the prerequisites. However I fell upon a makefile like this one: ``` SVR_OBJECT_FILES = server.o\ server_func.o CLT_OBJECT_FILES = client.o CFLAGS = -Wall -Werror -W CC = gcc all: client/client server/serveur client/client: $(CLT_OBJECT_FILES) server/serveur: $(SVR_OBJECT_FILES) client/client server/serveur: @mkdir -p $(dir $@) $(CC) $(CFLAGS) $^ -o $@ %.o: %.c $(CC) -c $< clean: rm -f client/client server/serveur *.o ``` Which works fine so my question is : How can the command below can link the right object files while the $^ variable is refering no preprerequisites at all. (the rule has no prerequisites) ``` $(CC) $(CFLAGS) $^ -o $@ ```