What is the difference between structural Verilog and behavioural Verilog?
verilog
Solution
There is no strict definition of these terms, according to the IEEE Std. However, customarily, structural refers to describing a design using module instances (especially for the lower-level building blocks such as AND gates and flip-flops), whereas behavioral refers to describing a design using `always` blocks.
Gate netlists are always structural, and RTL code is typically behavioral. It is common for RTL to have instances of clock gates and synchronizer cells.
Problem
As in the title, what are the main differences between structural and behavioural Verilog?