verilog always @(posedge) failing in uart

Question

I'm learning verilog and I think there is something that I must not understand about always @* and always (@posedge clk, ...) Here is a piece of code supposed to send bits via uart. It fails at synthesization. The error is " The logic for does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release." (and 3 other errors for , and ) If I change the always @(...) by always @*, things fail in the next step ("implement design") because things are not connected. In the book that I have, they implement an fsmd with an always (posedge clk) for the state, and always @* for the other logic, but I don't understand why this doesn't work. On another forum, I read that the error could come from too complicated conditions. But I have simplified things too (not code the code here but basically I removed the case(state) and the ifs to have single line assignments with ? : or binary conditions, but it…

Accepted Answer

The error:

```
The logic for does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
```

Is referring to the fact that the synthesis tool does not have any hardware cells to use which match your description.

What hardware do you want from :

```
always @(posedge baud_clk, posedge send_tick)
```

This looks like you want a flip-flop with an enable signal. The enable signal (send_tick) should be 1 clock period wide. This is then used to select the path of logic on a clock edge. not as an alternative trigger.

I think that this is all you really need:

```
always @(posedge baud_clk) begin
  case (state)
    IDLE:
      if (send_tick) begin
        //...
      end
     //...
   endcase
end
```

If `send_tick` is from another clock domain then you will need to do some clock domain crossing to turn it it to a clock wide pulse on the `baud_clk`.

You may be getting confused with blocks which have multiple triggers, they are normally a clk and reset. A `negedge reset_n` or `posedge reset` are often added for reset (initialisation) conditions.

If adding a reset :

```
always @(posedge baud_clk or negedge reset_n) begin
  if (~reset_n) begin
    //reset conditions
    state <= IDLE;
    //...
  end
  else begin
    // Standard logic
  end
end
```

You will notice that there is a very definite structure here, if reset else ... The synthesis tools recognise this as a flip-flop with an asynchronous reset. The data in the reset condition is also static, typically setting everything to zero.

verilog always @(posedge) failing in uart

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