VHDL std_logic_vector indexing with "downto"

indexing, vhdl

Solution

The assignment `X downto Y => 'A'` is correct when A is a element of array. For example, this snippet is correct:

1 downto 0 => '1',

And this snippet is wrong:

1 downto 0 => "01",

Therefore, your assignment is illegal. As your code, you can assign as:

DataOut <= (                        5 downto 3 =>'1',     
                                    2 downto 1 =>'0',     
                                    0 => '1',  
                                    others=>'0' 
                                    );

If you want to access/assign by a feild of array, you can use concatenation:

DataOut <= Something_0 & Something_1 & "01";

While `Something_*` is `std_logic_vector`

Problem

I would like to set bits of a std_logic_vector separately in order to easily set comments for individual bits or group of bits. Here is what I have: ``` signal DataOut : std_logic_vector(7 downto 0); ... DataOut <= ( 5=>'1', -- Instruction defined 4=>'1', -- Data length control bit, high=8bit bus mode selected 3=>'1', -- Display Line Number ctrl bit, high & N3 option pin to VDD=3 lines display 2=>'0', -- Double height font type control byte, not selected 1 downto 0=>"01", -- Select Instruction table1 others=>'0' -- for bits 6,7 ); ``` However, I've a problem with the "downto" statement, I get the following error using Xilinx ISE: ``` Type std_ulogic does not match with a string litteral ``` Any solution to avoid using the equivalent ``` 1=>'0', 0=>'1', ``` and to allow me to set bits by block?

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