Low Latency FWFT Fifo in Verilog

Question

I have the below code in which I try to implement a low latency first word fall-through fifo in verilog. ``` reg [width-1:0] mem [depth-1:0]; always @ (posedge clk) begin if (wr_en) begin mem[wr_pointer[address_width-1:0]] <= #1 din; end end assign #1 dout = mem[rd_pointer[address_width-1:0]]; always @ (posedge clk) begin if (reset) begin wr_pointer <= #1 0; end else if (wr_en) begin wr_pointer <= #1 wr_pointer + 1'b1; end end always @ (posedge clk) begin if (reset) begin rd_pointer <= #1 0; end else if (rd_en) begin rd_pointer <= #1 rd_pointer + 1'b1; end end ``` I synthesize it and receive the following message: ``` INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_mem> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Pl…

Accepted Answer

The line below is your asynchronous read:

```
assign #1 dout = mem[rd_pointer[address_width-1:0]];
```

Change it to something like the code below to make it synchronous.

```
reg [width-1:0] dout;
always @ (posedge clk) begin
   if (reset) begin
      dout <= #1 0;
   end else if (rd_en) begin
      dout <= #1 mem[rd_pointer[address_width-1:0]]
   end
end
```

The asynchronous read you had means that all the words in the memory must be available at any time, as the memory address could potentially change at any time (not just at a clock edge).

Since the asynch read needs access to all memory words, the FPGA can't use an on-chip RAM. An on-chip RAM has a read bus which can only access one word in the memory, and changes on a clock edge. So builds the memory instead out of a bunch of LUTs. In that case, you can think of the memory as build from a 2D array of flip-flops, and now it can wire up to all the words.

Low Latency FWFT Fifo in Verilog

Solution

Problem