$display every time $monitor works in Verilog
verilog
Solution
I do not think that behaviour is possible with monitor, but you could always just display when `a` changes:
always @(a) begin
$display("a=%h, b=%h",a,b);
end
Problem
In a Verilog testbench I have a `$monitor` statement that looks something like this: ``` initial begin $monitor("a=%h, b=%h",a,b) end ``` This means that both `a` and `b` are in the monitor's sensitivity list. What I actually want to do is just monitor changes to `a`, and when `a` changes display `b`'s value. I can't figure out how to do this. Is there an easy way?