One makefile for two compilers

c, c++, cross-compiling, g++, gnu-make

Solution

You can assign/append variables for specific targets by using the syntax target:assignment on a line. Here is an example:

native: CC=cc
native:
    echo $(CC)

cross: CC=arm-linux-gnueabihf-g++
cross:
    echo $(CC)

calling

make native

(or just `make`, here) prints

echo cc
cc

and calling

make cross

prints

echo arm-linux-gnueabihf-g++
arm-linux-gnueabihf-g++

So you can use your usual compilation line with $(CC)

Problem

I have two makefiles, for native and cross compilation. The only difference between them is compiler name: ``` # makefile CC = g++ ... ``` ``` # makefile-cc CC = arm-linux-gnueabihf-g++ ... ``` To make native compilation, I execute `make`, to make cross-compilation, I execute `make -f makefile-cc`. I want to have one `makefile`, which should be executed using `make` for native compilation, and `make cross` for cross-compilation. What is correct syntax to do this, something like: ``` # makefile (C-like pseudo-code) if cross CC = arm-linux-gnueabihf-g++ else CC = g++ ```

Original source