$size, $bits, verilog
arrays, system-verilog, verilog
Solution
`$size` shall return the number of elements in the dimension, which is equivalent to `$high - $low + 1`. It is relative to the dimension, not only bit counts. If the type is 1D packed array or integral type, it is equal to `$bits`.
`$bits` system function returns the number of bits required to hold an expression as a bit stream.
$bits ( [expression|type_identifier] )
It returns 0 when called with a dynamically sized type that is currently empty. It is an error to use the `$bits` system function directly with a dynamically sized type identifier.
I have no idea about your question, `c <= [($size(a)+$size(b)-1]-:$bits(b)];`. Is it a valid expression in RHS? Are you talking about the array range expression, `[n +: m]` or `[n -: m]` ?
Problem
What is the difference between `$size` and `$bits` operator in verilog.? if I've variables, `[9:0]a`,`[6:0]b`,`[31:0]c`. ``` c <= [($size(a)+$size(b)-1]-:$bits(b)]; ``` What will be the output at 'c' from the above expression?