How to do SystemVerilog-style bit vector slice assignment in C++?

bitset, c++, system-verilog

Solution

Now you are using SystemC, why don't you use sc_bv<> to represent HDL signals natively? Because SystemC has a set of data type to represent HDL bit/logic-wise and word logical operators, it should be more easy to mapping SystemVerilog/Verilog data types to C/C++ code.

sc_bv<4> reg1;
sc_bv<16> reg2;
reg1 = reg2.range(7,4);

Problem

I am porting some SystemVerilog code to SystemC/C++. I am using std::bitset to represent bit vectors, but I can see already it falls short of providing methods to access a slice. For example, if I want to set reg1 to bits 4-8 of reg2 with the SystemVerilog code: ``` bit [3:0] reg1; bit [15:0] reg2; reg1 = reg2[7:4]; ``` How could I do this with std::bitset? ``` bitset<4> reg1; bitset<16> reg2; reg1[0] = reg2[4]; reg1[1] = reg2[5]; reg1[2] = reg2[6]; reg1[3] = reg2[7]; ``` Is there a better way?

Original source