What does wildcard mean in makefile?
makefile
Solution
Suppose you have two source files. `foo.c` and `bar.c`.
program_C_SRCS:=$(wildcard *.c) # 1 line
The `wildcard` function is Make syntax. The variable `program_C_SRCS` will now have the value `foo.c bar.c` (maybe not in that order).
program_C_OBJ:=$(program_C_SRCS:.c=.o) # 2 line
This is a substitution reference. It transforms text, replacing one substring with another. The variable `program_C_OBJ` now has the value `foo.o bar.o`.
Problem
I found the following lines in a makefile tutorial, but I have some problem with the bold lines. In 1 line, if I write ``` program_C_SRCS:=$(*.c) ``` it does not work. So please tell me what is wildcard word in doing here. Is this word is specific to the makefile only? In tutorial it is written that second line will perform the test substitution. Can anyone tell me something about this text substitution? Please excuse me if my questions are very basic because I am new to make filestuff. link of tutorial ``` CC:=g++ program_NAME:=myprogram **program_C_SRCS:=$(wildcard *.c)** # 1 line program_CXX_SRCS:=$(wildcard *.cc) **program_C_OBJ:=$(program_C_SRCS:.c=.o)** # 2 line program_CXX_OBJ:=$(program_CXX_SRCS:.c=.o) program_OBJ:= $(program_C_OBJ) $(program_CXX_OBJ) ```