always @* block with a single non-blocking assignment - good, bad or irrelevant?
verilog
Solution
Irrelevant but bad practise.
I doubt that the single assignment causes any side effects. The always block will trigger for any change on the right hand side, updating in_ready. There is nothing to block, so non-blocking will not cause issues.
If a larger design had :
always @* begin
in_ready <= out_ready || ~out_valid ;
other_ready <= in_ready || other_ready ;
end
I am not too sure, as it is combinatorial it might just take an extra delta step to resolve.
Problem
The general rule of thumb mentioned in all of books I have read so far is that you have to use non-blocking assignments in always blocks that are driven by the raising or falling edge of the clock. On a contrary, blocking assignments must be used for combinatorial logic description. This rule makes sense to me and authors of examples follow it thoroughly. However, I spotted the following piece of Verilog in one of the production code: ``` always @* begin in_ready <= out_ready || ~out_valid; end ``` Note that non-blocking assignment `<=` is being used. I don't think it makes any difference in this case because there are no multiple assignments. However, I cannot seem to find any explanation for this. So the question is - does it or does not make any difference, both in the scope of a given always block and as part of the larger design?