Bitwise ANDING Of Two STD_LOGIC_VECTORS

Question

Hey I was wondering if it was at all possible in VHDL to AND two `STD_LOGIC_VECTORS` together. For example, I'm writing a VHDL program that will output a character to a VGA monitor. I have a vector `PixelRow: IN STD_LOGIC_VECTOR(9 DOWNTO 0)` and `PixelColumn: IN STD_LOGIC_VECTOR(9 DOWNTO 0)`. What I'm trying to do is have a `STD_LOGIC` Output that takes the two pixel vectors and ANDs them with another vector eg. ``` Output <= (PixelRow AND NOT "0000000000") OR (PixelColumn AND NOT "0000000000") OR (PixelRow AND NOT "0111011111") OR (PixelColumn AND NOT "1001111111"); ``` This code I'm hoping can be used to simplify the following code: ``` Output <= ((NOT PixelRow(0) AND NOT PixelRow(1) AND NOT PixelRow(2) AND NOT PixelRow(3) AND NOT PixelRow(4) AND NOT PixelRow(5) AND NOT PixelRow(6) AND NOT PixelRow(7) AND NOT PixelRow(8) AND NOT PixelRow(9))) OR ((NOT PixelRow(0) AND PixelRow(1) AND PixelRow(2) AND PixelRow(3) AND NOT PixelRow(4) AND PixelRow(5) AND PixelRow(6) AND PixelRow(7) AND P…

Accepted Answer

It is not clear to me what you need to and/or, and what you need to reduce to a single bit.

Sure there are the `and` and `or` bit-wise vector operators which return a vector of the same size.

If you need to test equality/inequality between `PixelRow` and `"0000000000"`, then you can write either: `PixelRow /= "0000000000"` or `PixelRow = "0000000000"`.

If you need to and-reduce a vector `vect : std_logic_vector(7 downto 0)` to a single bit `bit : std_logic`, the easiest way is probably to use a process:

```
process (vect) is
    variable tmp : std_logic;
begin
    tmp := '1';
    for I in 7 downto 0 loop
        tmp := tmp and vect(I);
    end loop;
    bit <= tmp;
end process;
```

If you need to do this frequently then you can define a `function` rather than a `process` to do this.

Bitwise ANDING Of Two STD_LOGIC_VECTORS

Solution

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