Is it possible to write type-generic entities in VHDL?
generics, type-parameter, vhdl
Solution
Yes, and implementing a Queue is one of the classic reasons to do it!
This has been in VHDL since VHDL-2008. Tool support is variable as of mid-2012. Talk about a slow-moving industry!
- Aldec supports it completely.
- Modelsim has partial support - can't find a public link to their capabilities. If you have it installed, it's in /technotes/vhdl2008.note
- Xilinx (XST/ISIM) doesn't support it, or even VHDL-2002. I can't find a simple link, but these PDFs have sections on VHDL compatibility, which only talk of VHDL-1993.
- Altera's tools have partial support, but not for type generics
Problem
So, I recently inherited some VHDL code, and my first reaction was, "VHDL has structs, why do they use bit-vectors everywhere?" And then I realized this is because there does not seem to be any way to write anything like this: ``` entity Queue is generic ( EL : type ); port ( data_in : EL; data_out : EL; ... ); end entity Queue; ``` I really wish this were possible. Is there anything even remotely approximating it? Even if I have to retype the entity or component declarations, just some way to avoid retyping the architecture definition for every (modulo a generic width) type?