How to "slice" an std_logic_vector in VHDL?
syntax, vhdl
Solution
You can directly assign them:
firstpart <= allparts(15 downto 8);
secondpart <= allparts(7 downto 0);
...or if firstpart and secondpart are simply alternate ways to refer to part of the allparts signal, you may want to use an alias:
alias firstpart is allparts(15 downto 8);
alias secondpart is allparts(7 downto 0);
Problem
I'm developing a little thing in VHDL and am quite new to it. I'm having trouble figuring out how to slice a bigger std_logic_vector into a smaller one. For instance I have 3 signals: ``` signal allparts: std_logic_vector(15 downto 0); signal firstpart: std_logic_vector(7 downto 0); signal secondpart: std_logic_vector(7 downto 0); ``` Basically, what I want is to assign bits 15 through 8 to `secondpart` and bits 7 through 0 to `firstpart`. How exactly would I "slice" a vector like this without assigning individual bits