Signals and ports on which side of the "arrow" =>
vhdl
Solution
`<=` is an assignment - specifically a signal assignment, driving a signal with a value from somewhere else. For a physical analogy, the thing on the right hand side drives a value onto the left hand side.
`=>` is a port mapping from a pin to a signal. This is not an assignment - the physical analogy might be soldering a pin to a wire.
You can only do "soldering" to instantiations, so `=>` mapping only happens inside a `port map`. And there, "pins" always go on the left (because that's what the language rules say), which is why you can't do `x <= port_a` in a `port map`.
Problem
How do I know where the port/signal/value should be placed on which side of the arrows? I noticed that by switching `port_a => x` to `x <= port_a` which seems very equal, I got an error. Also, `x => port_a` doesn't work. I even do not know which way the arrows should point.