Verilog, FPGA, use of an unitialized register

Question

I have a question about what seems to me odd behavior of an AGC/SPI controller I'm working on. It's done in Verilog, targeting a Xilinx Spartan 3e FPGA. The controller is a FSM that relies on external inputs to start. The state of the FSM is stored in state_reg which is not explicitly initialized, as I thought an uninitialized register would default to zero. When I implemented the controller the FSM would not run. Monitoring the SPI bus I observed no activity. To monitor the FSM i routed the state_reg to an output bus that went to an LED bank. That is what the line assign data_out = state_reg is doing. I found though that when I did this the FSM an AGC/SPI controller operated correctly as observed on the SPI bus. It seems that what is happening is that state_reg is in an undetermined state when it initializes and hence the FSM is never in any state so it doesn't run. But by assigning state_reg to an output it initialized to 00000000 as I expected it to do from the beginning. So my que…

Accepted Answer

I answer in the context of FPGAs (I have most experience with Xilinx FPGAs); I disagree with Tim's answer.

When an FPGA is programmed and initialized, many internal resources are initialized to a known state. This includes all flip flops and block rams. By adding blanket reset logic throughout your design, you may make it significantly more complicated than it needs to be, if you could otherwise count on internal elements initializing to a known state. High fanout reset nets can make implementation of your design much more difficult for the router, and mapping your design into slices is also complicated by your choice of resets - especially asynchronous ones.

My suggestions:

- Use initialization values for your registers. Double check Xilinx XST documentation for the version you are using for supported syntax. Contrary to widely held belief, initialization values will be honored in most cases. The side benefit of doing this, is that the initial state of your chip will match the initial state of your simulation.

- Only reset necessary control signals and leave your datapath registers alone to allow more efficient mapping (for example, a pipeline into a shift register).

Verilog, FPGA, use of an unitialized register

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